The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a cross-sectional view of a dual-edged memory cell 100 according to the prior art is shown. In various implementations, the dual-edged memory cell 100 may be nitride-based and may include a nitride read-only memory (NROM) transistor from Saifun Semiconductors, Ltd. The dual-edged memory cell 100 is referred to hereinafter as the transistor 100.
The transistor 100 includes a p-doped substrate 102, a first n+ doped region (“right contact”) 104, which can be used as a source or drain. The transistor 100 also includes a second n+ doped region (“left contact”) 106, which can be used as a drain or source. The transistor 100 further includes a first gate dielectric layer 108, a trapping material (such as nitride) layer 110, a second gate dielectric layer 112, and a polysilicon gate 114.
The transistor 100 can store charge in two regions, generally depicted in FIG. 1 as two circular regions: a left region 120 and a right region 122. The amount of charge stored in the left and right regions 120 and 122 affects the threshold voltage of the transistor 100, which is a property that can be used to store data.
Because the transistor 100 is substantially symmetrical, right and left contacts 104 and 106 can be used interchangeably as source and drain. In order to program the right region 122, a positive voltage is applied to the gate 114 and to the right contact 104, while the left contact 106 is held at ground. Electrons then travel from the left contact 106 to the right contact 104, and some gain sufficient energy to pass through the first gate dielectric layer 108 and become trapped in the nitride layer 110. The charge may be trapped within the right region 122.
The charge trapped in the right region 122 has a dramatic effect on the threshold voltage of the transistor 100 when reading in a direction opposite to the programming direction. In other words, a voltage is applied to the gate 114 and to the left contact 106, while the right contact 104 is held at ground. This voltage is generally less than the voltage used for programming the transistor 100. The amount of current that then flows through the transistor 100 is indicative of the threshold voltage of the transistor 100 in the read direction, and thus the amount of charge trapped in the right region 122.
The arrows below the transistor 100 indicate the direction of flow of electrons during programming and reading operations for each of the left and right regions 120 and 122. The voltages for programming and reading are reversed for the left region 120. For instance, a program is performed for the right region 122 when electrons flow from the left contact 106 to the right contact 104. This is accomplished by holding the right contact 104 at a higher potential than the left contact 106.
A read of the right region 122 is performed by holding the left contact 106 at a higher potential so that electrons will flow to the left contact 106 during the read. For the left region 120, a program operation involves holding the left contact 106 at a higher potential than the right contact 104. A read of the left region 120 can be performed by holding the right contact 104 at a higher potential than the left contact 106.
Referring now to FIG. 2, a functional schematic of an array 150 of storage cells within a NAND flash memory according to the prior art is depicted. The array 150 includes top and bottom select transistors 152 and 154, which may be n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs). The array 150 also includes four NAND storage cells 156-1, 156-2, 156-3, and 156-4 connected in series between the bottom select transistor 154 and the top select transistor 152. The NAND storage cells 156 may be implemented as floating gate n-MOSFET devices.
A NAND storage cell, such as NAND storage cell 156-4, can be programmed by placing a large voltage, such as 20 volts, on the gate of NAND storage cell 156-4. The top select transistor 152 will also receive 20 volts at its gate, while the bottom select transistor 154 will have its gate grounded. The drain of the top select transistor 152 will also be grounded.
The gates of NAND storage cells 156-3, 156-2, and 156-1, which will not be programmed, are held at a voltage, such as 5 volts, that is enough to turn the transistor on without programming it. Electrons are trapped in the floating gate of NAND storage cell 156-4, thereby changing its threshold voltage.
Reading NAND storage cell 156-4 involves turning on the other NAND storage cells 156-3, 156-2, and 156-1 by applying a turn-on voltage, such as 5 volts. The top and bottom select transistors 152 and 154 are also turned on. The gate of NAND storage cell 156-4 is held at a voltage where a changed threshold voltage will be evidenced as a large change in drain current.
A predetermined current, such as an average of currents sunk by the NAND storage cell 156-4 at different threshold voltages, is placed into the drain of the top select transistor 152. If this current is higher than the current being sourced by NAND storage cell 156-4, the voltage at the drain of the top select transistor 152 will increase; otherwise, the voltage at the drain of the top select transistor 152 will decrease. This voltage level can be measured to infer the threshold voltage of the NAND storage cell 156-4, and thus the program state of NAND storage cell 156-4.
Referring now to FIG. 3, a functional block diagram of a memory 200 according to the prior art is depicted. The memory 200 includes storage cell arrays 202 and a controller 204. The storage cell arrays 202 may be composed of such devices as dual-edged memory cells, as described in FIG. 1, and NAND storage cells, as described in FIG. 2. The controller 204 communicates outside the memory 200 with an external device, and programs, erases, and reads the storage cell arrays 202.